In computer architecture, the iron law of processor performance (or simply iron law of performance) describes the performance trade-off between complexity and the number of primitive instructions that processors use to perform calculations.[1] This formulation of the trade-off spurred the development[citation needed] of Reduced Instruction Set Computers (RISC) whose instruction set architectures (ISAs) leverage a smaller set of core instructions to improve performance. The term was coined by Douglas Clark[2] based on research performed by Clark and Joel Emer in the 1980s.[3]
Explanation
The performance of a processor is the time it takes to execute a program:
. This can be further broken down into three factors:[4]
![{\displaystyle \mathrm ((\frac {Instructions}{Program))\times {\frac {ClockCycles}{Instruction))\times {\frac {Time}{ClockCycles))} }](https://wikimedia.org/api/rest_v1/media/math/render/svg/dd020f1076a99e725f8aaf43cc85b8f5310e743c)
Selection of an instruction set architecture affects
, whereas
is largely determined by the manufacturing technology. Classic Complex Instruction Set Computer (CISC) ISAs optimized
by providing a larger set of more complex CPU instructions. Generally speaking, however, complex instructions inflate the number of clock cycles per instruction
because they must be decoded into simpler micro-operations actually performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is close to what is produced for a comparable RISC ISA.[5] The iron law of processor performance makes this trade-off explicit and pushes for optimization of
as a whole, not just a single component.
While the iron law is credited for sparking the development of RISC architectures,[citation needed] it does not imply that a simpler ISA is always faster. If that were the case, the fastest ISA would consist of simple binary logic. A single CISC instruction can be faster than the equivalent set of RISC instructions when it enables multiple micro-operations to be performed in a single clock cycle. In practice, however, the regularity of RISC instructions allowed a pipelined implementation where the total execution time of an instruction was (typically) ~5 clock cycles, but each instruction followed the previous instruction ~1 clock cycle later [citation needed]. CISC processors can also achieve higher performance using techniques such as modular extensions, predictive logic, compressed instructions, and macro-operation fusion.[6][5][7]